S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x06A, 0x16A, 0x26A, 0x36A, 0x46A, 0x56A, 0x66A, 0x76A:
RXCP HCS Error Count
Bit
Type
R
R
R
R
R
R
R
R
Function
HCS[7]
HCS[6]
HCS[5]
HCS[4]
HCS[3]
HCS[2]
HCS[1]
HCS[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
HCS[7:0]:
The HCS[7:0] bits indicate the number of HCS error events that occurred during the last
accumulation interval. The contents of these registers are valid a maximum of 40 RCLK
periods after a transfer is triggered by a write to one of RXCP's performance monitor.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all
channels and APS links.
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
229
PMC [ PMC-SIERRA, INC ]
