S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x003: S/UNI-8x155 Clock Monitors
Bit
Type
Function
Unused
Unused
RCLKA
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
R
TCLKA
Unused
RFCLKA
TFCLKA
REFCLKA
R
R
R
This register provides activity monitoring of the S/UNI-8x155 clocks. When a monitored clock
signal makes a low to high transition, the corresponding register bit is set high. The bit will
remain high until this register is read, at which point, all the bits in this register are cleared. A
lack of transitions is indicated by the corresponding register bit reading low. This register
should be read at periodic intervals to detect clock failures.
REFCLKA:
The REFCLK active (REFCLKA) bit monitors for low to high transition on the REFCLK
reference clock input. REFCLKA is set high on a rising edge of REFCLK and is set low
when this register is read.
TFCLKA:
The TFCLK active (TFCLKA) bit monitors for low to high transition on the TFCLK system
interface clock input. TFCLKA is set high on a rising edge of TFCLK and is set low when
this register is read.
RFCLKA:
The RFCLK active (RFCLKA) bit monitors for low to high transition on the RFCLK
system interface clock input. RFCLKA is set high on a rising edge of RFCLK and is set
low when this register is read.
RCLKA:
The RCLK active (RCLKA) bit monitors for low to high transition on the RCLK receive
line rate clock. RCLKA is set high on a rising edge of RCLK and is set low when this
register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
113
PMC [ PMC-SIERRA, INC ]
