S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x100: S/UNI-8x155 Master Interrupt Status #1
Bit
Type
R
R
R
R
R
R
R
R
Function
RDLLI
RUL3I
TDLLI
TUL3I
TAPSI
CSPII
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
STALI
RAPSI
When the interrupt output INTB goes low, this register allows the source of the active interrupt
to be identified down to the block level. Further register accesses are required for the block in
question to determine the cause of an active interrupt and to acknowledge the interrupt source.
RAPSI:
The RAPSI bit is a logic one when an interrupt request is active from the receive APS
interfaces. The APS Interrupt Status #1 and APS Interrupt Status #2 registers must be read
in order to determine the block with the active interrupt source.
STALI:
The STALI bit is a logic one when an interrupt request is active from the STAL blocks.
Each Channel Cross Connect Control registers must be read to identify the channel STALs
with the active interrupt source.
CSPII:
The CSPI bit is a logic one when an interrupt request is active from the CSPI block. The
CSPI interrupt sources are enabled in the CSPI Clock Synthesis Configuration register.
TAPSI:
The TXAPSI bit is a logic one when an interrupt request is active from the APS interfaces.
The APSI interrupt sources can be determined by the APS Interrupt Status and APS FIFO
Configuration and Status registers.
TUL3I:
The TUL3I bit is a logic one when an interrupt request is active from the TUL3 block. The
TUL3 interrupt sources are enabled in the TUL3 Interrupt Status/Enable #1 and
Interrupt Status/Enable #2 registers.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
115
PMC [ PMC-SIERRA, INC ]
