S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x001: S/UNI-8x155 Master Configuration
Bit
Type
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
TIP
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
TIP:
The TIP bit is set to a logic one when the performance monitor registers are being loaded.
Writing to the S/UNI-8x155 Master Reset and Identity register (0x000) initiates an
accumulation interval transfer and loads all the performance monitor registers in the RSOP,
RLOP, RPOP, SSTB, SPTB, RXCP, TXCP, RXFP, TXFP and RAOP blocks.
TIP remains high while the transfer is in progress, and is set to a logic zero when the
transfer is complete. TIP can be polled by a microprocessor to determine when the
accumulation interval transfer is complete.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
112
PMC [ PMC-SIERRA, INC ]
