S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x101: S/UNI-8x155 Master Interrupt Status #2
Bit
Type
R
R
R
R
R
R
R
R
Function
CHNLI[7]
CHNLI[6]
CHNLI[5]
CHNLI[4]
CHNLI[3]
CHNLI[2]
CHNLI[1]
CHNLI[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
When the interrupt output INTB goes low, this register allows the source of the active interrupt
to be identified down to the channel level. Further register accesses are required for the channel
in question to determine the cause of an active interrupt and to acknowledge the interrupt
source.
CHNLI[7:0]:
A channel interrupt CHNLI[7:0] bit is a logic one when an interrupt request is active from
the corresponding channel. A channel’s Reset/Interrupt Status #1 register must be read in
order to determine the block with the active interrupt source.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
117
PMC [ PMC-SIERRA, INC ]
