S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
11.2 Registers
Register 0x000: S/UNI-8x155 Master Reset and Identity
Bit
Type
R/W
R
R
R
R
R
R
R
Function
RESET
TYPE[3]
TYPE[2]
TYPE[1]
TYPE[0]
ID[2]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
1
ID[1]
ID[0]
This register allows the revision number of the S/UNI-8x155 to be read by software permitting
graceful migration to newer, feature-enhanced versions of the S/UNI-8x155.
In addition, writing to this register simultaneously loads all the performance monitor registers in
all channels (equivalent to writing to 0x007, 0x107, 0x207 and 0x307). The TIP register in
0x001 is set high while the performance registers are loaded and clears when the transfer is
done.
ID[2:0]:
The ID bits can be read to provide a binary S/UNI-8x155 revision number.
TYPE[3:0]:
The TYPE bits can be read to distinguish the S/UNI-8x155 from the other members of the
S/UNI family of devices.
RESET:
The RESET bit allows the S/UNI-8x155 to be reset under software control. If the RESET
bit is a logic one, the entire S/UNI-8x155 is held in reset. This bit is not self-clearing.
Therefore, a logic zero must be written to bring the S/UNI-8x155 out of reset. Holding the
S/UNI-8x155 in a reset state places it into a low power, stand-by mode. A hardware reset
clears the RESET bit, thus negating the software reset. Otherwise, the effect of a software
reset is equivalent to that of a hardware reset.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
111
PMC [ PMC-SIERRA, INC ]
