PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
InputTransmit
Data
Bit Settings
XCLK Freq
Affect on Output
Transmit Data
Backplane
transmit data
timed to
>2.048MHz
backplane clock.
BTCLK is
HSBPSEL =1
XCLKSEL =0
OCLKSEL1 =0
OCLKSEL0 =0
37.056MHz
Jitter attenuated.
TCLKO is a
smooth
1.544MHz.
TCLKO
referenced to
externally
"gapped" transmit
clock.
PLLREF1
PLLREF0
=0
=X
externally
"gapped".
TCLKISEL =0
TCLKO
referenced to
RCLKO.
SMCLKO
PLLREF1
PLLREF0
PLLREF1
PLLREF0
=0
=1
=0
=1
=1
TCLKO
referenced to
TCLKI.
Backplane
transmit data
timed to BTCLK.
HSBPSEL =0
XCLKSEL =0
OCLKSEL1 =1
OCLKSEL0 =X
37.056MHz
No jitter
attenuation.
TCLKO is equal
to internal
transmit clock,
either BTCLK,
gapped BTCLK,
or RCLKO.
PLLREF1
PLLREF0
=X
=X
TCLKISEL =0
SMCLKO =0
Same as above.
12.352MHz
XCLKSEL =1
TCLKISEL =1
SMCLKO
=1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
82
PMC [ PMC-SIERRA, INC ]
