PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 1DH: ELST Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
SLIPE
X
X
X
X
X
0
R/W
R
SLIPD
SLIPI
X
X
R
SLIPE:
The SLIPE bit position enables generation of an interrupt on the
microprocessor INTB pin when a slip event occurs.
SLIPI:
The SLIPI bit indicates whether a slip event has occurred since the last read
of the Enable/Status register. SLIPI is a logic 1 if a slip has occurred; SLIPI is
a logic 0 is no slip has occurred. The SLIPI bit is cleared after the register is
read.
SLIPD:
The SLIPD bit indicates the direction of the last slip when SLIPI is a logic 1. If
a slip has occurred and the SLIPD bit is a logic 1 then the slip was due to the
frame buffer becoming full. If a slip has occurred and the SLIPD bit is a logic
0 then the slip was due to the frame buffer becoming empty.
Upon reset of the T1XC, SLIPE is set to logic 0, disabling generation of an interrupt.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
112
PMC [ PMC-SIERRA, INC ]
