PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 1AH: DJAT Output Clock Divisor (N2) Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N2[7]
N2[6]
N2[5]
N2[4]
N2[3]
N2[2]
N2[1]
N2[0]
0
0
1
0
1
1
1
1
This register defines an 8-bit binary number, N2, which is one less than the
magnitude of the divisor used to scale down the DJAT smooth output clock
signal. The output clock divisor magnitude, (N2+1), is the ratio between the
frequency of the smooth output clock and the frequency applied to the phase
discriminator input. If the SYNC bit is set to logic 1 in Register 1Bh, the Clock
Divisors N1 and N2 (Registers19h and 1Ah) must be set such that N1+1 and
N2+1 are both multiples of 48.
Writing to this register will reset the PLL and, if the SYNC bit is high, will also
reset the FIFO.
Upon reset of the T1XC, the default value of N2 is set to decimal 47 (2FH).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
108
PMC [ PMC-SIERRA, INC ]
