PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 21H: FRMR Interrupt Enable
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
ACCEL
COFAE
FERE
X
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BEEE
SFEE
MFPE
INFRE
This register selects which of the MFP, COFA, FER, BEE, SFE, or INFR events
generates an interrupt on the microprocessor INTB pin when their state changes
or their event condition is detected.
ACCEL:
The ACCEL bit is used for production test purposes only. THE ACCEL BIT
MUST BE PROGRAMMED TO LOGIC 0 FOR NORMAL OPERATION.
COFAE:
The COFAE bit enables the generation of an interrupt when the frame find
circuitry determines that frame alignment has been achieved and that the
new alignment differs from the previous alignment. When COFAE is set to
logic 1, the declaration of a change of frame alignment is allowed to generate
an interrupt. When COFAE is set to logic 0, a change in the frame alignment
does not generate an interrupt.
FERE:
The FERE bit enables the generation of an interrupt when a framing bit error
has been detected. When FERE is set to logic 1, the detection of a framing
bit error is allowed to generate an interrupt. When FERE is set to logic 0, any
error in the framing bits does not generate an interrupt.
BEEE:
The BEEE bit enables the generation of an interrupt when a bit error event
has been detected. A bit error event is defined as framing bit errors for SF
formatted data, CRC-6 mismatch errors for ESF formatted data, Ft bit errors
for SLC®96 formatted data, and either framing bit errors or sync word errors
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
116
PMC [ PMC-SIERRA, INC ]
