PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
FMS1,FMS0:
The FMS1 and FMS0 bits select standard superframe, T1DM, or SLC®96
framing formats. A logic 00 in these bits enable the SF framing format; a logic
01 or 11 in these bit positions enable the T1DM framing format; a logic 10 in
these bit positions enable the SLC®96 framing format.
When ESF is selected (ESF bit set to logic 1), the FMS1 and FMS0 bits
select the data rate and the source channel for the facility data link data. A
logic 00 in these bits enable the FRMR to receive FDL data at the full 4 kHz
rate from every odd frame. A logic 01 in these bits enable the FRMR to
receive FDL data at a 2 kHz rate from frames 3,7,11,15,19,23. A logic 10 in
these bits enable the FRMR to receive FDL data at a 2 kHz rate from frames
1,5,9,13,17,21. Logic value 11 is reserved and should not be used.
The valid combinations of the ESFFA, ESF, FMS1, and FMS0 bits are
summarized in the table below:
Table 9
ESF
- FRMR Frame Format Options
FMS1 FMS0
Mode
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Select SF framing format
Select T1DM framing format
Select SLC96 framing format
Select T1DM framing format
Select ESF framing format & 4 kHz FDL Data Rate
Select ESF framing format & 2 kHz FDL Data Rate
using frames 3,7,11,15,19,23.
1
1
1
1
0
1
Select ESF framing format & 2 kHz FDL Data Rate
using frames 1,5,9,13,17,21
RESERVED
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
115
PMC [ PMC-SIERRA, INC ]
