PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 1BH: DJAT Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
WIDEN
CENT
UNDE
OVRE
SYNC
LIMIT
X
X
1
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
This register controls the operation of the DJAT FIFO read and write pointers and
controls the generation of interrupt by the FIFO status.
WIDEN:
The WIDEN bit controls the width of the generated DSX-1 pulse from the
XPLS block. When WIDEN is set to logic 1, the high phase of one cycle of
the smooth, 12.352 MHz clock generated by the DJAT PLL is modified to be
nominally 27ns wider. This results in the XPLS producing an enhanced DSX-
1 pulse width. When WIDEN is set to logic 0, the smooth, 12.352MHz clock
from DJAT is not modified, resulting in DSX-1 pulses of minimum allowable
width. These narrow pulses reduce the amount of energy sourced by T1XC
into the line. The WIDEN bit has no effect when the DJAT PLL is not used
(i.e. the SMCLKO bit in register 7 is set to logic 1); if an enhanced width DSX-
1 pulse is desired under this condition, the externally applied 12.352MHz
clock phase must be explicitly modified before it is applied to the T1XC.
CENT:
The CENT bit allows the FIFO to self-center its read pointer, maintaining the
pointer at least 4 UI away from the FIFO being empty or full. When CENT is
set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data
bit period, and for the first 384 bit periods following an overrun or underrun
event. If an EMPTY or FULL alarm occurs during this 384 UI period, then the
period will be extended by the number of UI that the EMPTY or FULL alarm
persists. During the EMPTY or FULL alarm conditions, data is lost. When
CENT is set to logic 0, the self-centering function is disabled, allowing the
data to pass through uncorrupted during EMPTY or FULL alarm conditions.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
109
PMC [ PMC-SIERRA, INC ]
