PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 20H: FRMR Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
M2O[1]
M2O[0]
ESFFA
ESF
0
0
0
0
0
0
X
X
FMS1
FMS0
Unused
Unused
This register selects the framing format and the frame loss criteria used by the
FRMR.
M2O[1:0]:
The M2O[1:0] bits select the ratio of errored to total framing bits before declaring out of
frame in SF, SLC®96, and ESF framing formats. A logic 00 selects 2 of 4 framing bits in
error; a logic 01 selects 2 of 5 bits in error; a logic 10 selects 2 of 6 bits in error. In T1DM
framing format, the ratio of errored to total framing bits before declaring out of frame is
always 4 out of 12. A logic 11 in the M2O[1:0] bits is reserved and should not be used.
ESFFA:
The ESFFA bit selects one of two framing algorithms for ESF frame search in the
presence of mimic framing patterns in the incoming data. A logic 0 selects the ESF
algorithm where the FRMR does not declare inframe while more than one framing bit
candidate is following the framing pattern in the incoming data. A logic 1 selects the
ESF algorithm where a CRC-6 calculation is performed on each framing bit candidate,
and is compared against the CRC bits associated with the framing bit candidate to
determine the most likely framing bit position.
ESF:
The ESF bit selects either extended superframe format or enables the Frame Mode
Select bits to select either standard superframe, T1DM, or SLC®96 framing formats. A
logic 1 in the ESF bit position selects ESF; a logic 0 bit enables FMS1 and FMS0 to
select SF, T1DM, or SLC®96.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
114
PMC [ PMC-SIERRA, INC ]
