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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
When an accumulation interval is signaled by a write to the PMON register  
address space, the PMON transfers the current counter values into  
microprocessor accessible holding registers and resets the counters to begin  
accumulating error events for the next interval. The counters are reset in such a  
manner that error events occurring during the reset period are not missed.  
When counter data is transferred into the holding registers, an interrupt is  
generated, providing the interrupt is enabled. If the holding registers have not  
been read since the last interrupt, an overrun status bit is set. In addition, a  
register is provided to indicate changes in the PMON counters since the last  
accumulation interval.  
Whenever counter data is transferred into the holding registers, an interrupt is  
generated, providing the interrupt is enabled. If the holding registers have not  
been read since the last interrupt, an overrun status bit is set.  
9.24 DS3 Transmitter (DS3-TRAN)  
The DS3 Transmitter (DS3-TRAN) Block integrates circuitry required to insert the  
overhead bits into a DS3 bit stream and produce a B3ZS-encoded signal. The  
T3-TRAN is directly compatible with the M23 and C-bit parity DS3 formats.  
When configured for the C-bit parity application, all overhead bits are inserted.  
When configured for the M23 application, all overhead bits except the stuff  
control bits (the C-bits) are inserted; the C-bits are inserted by the upstream  
MX23 TSB.  
Status signals such as far end receive failure (FERF), the alarm indication signal,  
and the idle signal can be inserted when their transmission is enabled by internal  
register bits. FERF can also be automatically inserted on detection of any  
combination of LOS, OOF or RED, or AIS by the DS3-FRMR.  
A valid pair of P-bits is automatically calculated and inserted by the DS3-TRAN.  
When C-bit parity mode is selected, the path parity bits, and far end block error  
(FEBE) indications are automatically inserted.  
When enabled for C-bit parity operation, the FEAC channel is sourced by the  
XBOC bit-oriented code transmitter. The path maintenance data link messages  
are sourced by the TDPR data link transmitter.  
The DS3-TRAN supports diagnostic modes in which it inserts parity or path parity  
errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code  
violations, or all-zeros.  
PROPRIETARY AND CONFIDENTIAL  
81  
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