STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 69: T1 Egress Interface 2.048 MHz Clock Slave: External Signaling
Mode
CECLK
CEFP
ED[x]
Don't Care
Don't Care
Don't Care
F
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A B C D
Don't Care
A B C D
A B C D
A B C D
ESIG[x]
F-Bit or
Parity
Channel 1
Channel 2
Channel 3
"filler"
Channel 4
CECLK
CEFP
ED[x]
Ch24
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch23
Ch24
Ch1
ESIG[x]
The Egress Interface is configured for the 2.048 MHz Clock Slave: External
Signaling Mode by writing to EMODE[2:0] in theT1/E1 Egress Serial Interface
Mode Select register. The 2.048 MHz internally gapped clock mode is selected
by writing CECLK2M to logic 1 in the Master Egress Slave Mode Serial Interface
register. In the illustrated case, CEFP specifies frame alignment and is required
to pulse high for one cycle every frame. ESIG[x] should carry the signaling bits
for each channel in bits 5,6,7 and 8; the signaling bits will be inserted into the
data stream by the transmitter. If parity checking is enabled, a parity bit should
be inserted on ED[x] and ESIG[x] in the first bit of each frame. The values of the
don’t-care bits are not important, except that they will be used in the backplane
parity check if it is enabled.
Figure 70: T1 and E1 Egress Interface Clock Slave: Clear Channel Mode
ECLK[x]
ED[x]
8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
PROPRIETARY AND CONFIDENTIAL
194
PMC [ PMC-SIERRA, INC ]
