STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 73: T1 Ingress Interface Clock Master: NxChannel Mode
IFP[x]
Don't Care
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
ID[x]
ICLK[x]
Figure 74: E1 Ingress Interface Clock Master: NxChannel Mode
IFP[x]
Don't Care
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
ID[x]
ICLK[x]
Timeslot 1
Timeslot 31
The IMODE[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register
are programmed to select NxChannel mode. The RPSC ingress control bytes
are programmed to extract the desired channels. In Figure 73, the ingress
control bytes for T1 channels 2 and 24 are extracted. In Figure 74, the ingress
control bytes for E1 channels 31 and 1 are extracted. ICLK[x] is gapped so that it
is only active for those channels with the associated DTRKC bit set to 0. If either
IMFP or ALTIFP is set, then IFP[x] will pulse only during the appropriate frames.
When the IDE bit in the T1/E1 Serial Interface Configuration register bit is set,
then ID[x] is updated on the rising edge of ICLK[x] and the functional timing is
described by with ICLK[x] inverted.
Figure 75: T1 and E1 Ingress Interface Clock Master: Clear Channel Mode
I CLK[x]
I D[x]
8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
The Ingress Interface is configured for the Clock Slave: Clear Channel mode by
writing to IMODE[1:0] in the T1/E1 Ingress Serial Interface Mode Select register.
ID[x] is updated on the falling edge of the ICLK[x] input. When the IDE bit in the
T1/E1 Serial Interface Configuration register is set to logic 1, then ID[x] is
updated on the rising edge of ICLK[x], and the functional timing is described by
Figure 75 with the ICLK[x] signal inverted.
PROPRIETARY AND CONFIDENTIAL
196
PMC [ PMC-SIERRA, INC ]
