STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
13.7 Egress Serial Clock and Data Interface Timing
By convention in the following functional timing diagrams, the first bit transmitted
in each channel shall be designated bit 1 and the last shall be designated bit 8.
Each of the Ingress and Egress Master and Clock Modes apply to both T1 and
E1 configurations with the exception of the 2.048MHz T1 Clock Slave Modes.
Figure 61: T1 Egress Interface Clock Master: NxChannel Mode
Channel 24
Channel 1
Don't Care
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
ED[x]
ECLK[x]
Figure 62: E1 Egress Interface Clock Master : NxChannel Mode
Don't Care
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
ED[x]
ECLK[x]
Timeslot 25
Timeslot 23
The Egress Interface Options register is programmed to select NxChannel mode.
The TPSC egress control bytes are programmed to insert the desired channels.
In Figure 61, the egress control bytes for T1 channels 1 and 24 are configured to
insert these channels. In Figure 62, the egress control bytes for E1 channels 23
and 25 are configured to insert these channels. ECLK[x] is gapped so that it is
only active for those channels with the associated IDLE_CHAN bit cleared (logic
0). The remaining channels (with IDLE_CHAN set) contain the per-channel idle
code as defined in the associated Idle Code byte. When the EDE bit in the
T1/E1 Serial Interface Configuration register is set to logic 0, then ED[x] is
sampled on the falling edge of ECLK[x], and the functional timing is described by
Figure 61 with the ECLK[x] signal inverted.
Figure 63: T1 and E1 Egress Interface Clock Master: Clear Channel Mode
ECLK[x]
ED[x]
8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
PROPRIETARY AND CONFIDENTIAL
190
PMC [ PMC-SIERRA, INC ]
