STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 68: T1 Egress Interface 2.048 MHz Clock Slave: EFP Enabled Mode
CECLK
CEFP
ED[x]
Don't Care
Don't Care
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
F
EFP[x]
F-Bit or
Parity
Channel 1
Frame 1
Channel 2
Frame 1
Channel 3
Frame 1
Channel 4
Frame 1
"filler"
CECLK
CEFP
ED[x]
Ch24
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch23
Ch24
Ch1
EFP[x]]
The Egress Interface is configured for the Clock Slave: EFP Enabled Mode by
writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register.
The 2.048 MHz internally gapped clock mode is selected by writing CECLK2M to
logic 1 in the Master Egress Slave Mode Serial Interface register. In Figure 68,
CEFP is configured for superframe alignment by writing CEMFP to logic 1 in the
Master Egress Slave Mode Serial Interface register, so that the CEFP input must
pulse once every 12 or 24 frames (for SF and ESF, respectively) on the first F-bit
of the multiframe to specify superframe alignment, instead of once every frame
to specify frame alignment. If parity checking is enabled, a parity bit should be
inserted on ED[x] in the first bit of each frame. The EFP[x] output will pulse high
to mark the F-bit of each frame in order to indicate frame alignment to an
upstream device. EFP[x] may be configured to mark superframe alignment
instead by setting the EMFP bit in the T1/E1 Serial Interface Configuration
register. The values of the don’t-care bits are not important, except that they will
be used in the backplane parity check if it is enabled.
PROPRIETARY AND CONFIDENTIAL
193
PMC [ PMC-SIERRA, INC ]
