STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 78: T1 Ingress Interface 2.048 MHz Clock Slave: External Signaling
Mode
CICLK
CIFP
ID[x]
Don't Care
Don't Care
Don't Care
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7
1 2 3 4 5 6 7 8
A B C D
1 2 3 4 5 6 7 8
A B C D
F
8
Don't Care
ISIG[x]
A B C D
A B C D
F-Bit
or Parity
Channel 1
Channel 2
Channel 3
"filler"
Channel 4
CICLK
CIFP
ID[x]
Ch24
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch23
Ch 24
Ch1
ISIG[x]
The Ingress Interface is programmed for Clock Slave mode by setting the
IMODE[1:0] in the T1/E1 Ingress Serial Interface Mode Select register. The
2.048 MHz internally-gapped clock mode is selected by setting the CICLK2M bit
to logic 1 in the Master Ingress Slave Mode Serial Interface Configuration
register. ID[x] is timed to the active edge of CICLK, and is frame-aligned to CIFP.
CIFP need not be provided every frame. ID[x] and ISIG[x] may be configured to
carry a parity bit during the first bit of each frame. The values of the filler bits will
depend on the exact configuration of the TECT3, and they will be included in the
parity calculation.
PROPRIETARY AND CONFIDENTIAL
198
PMC [ PMC-SIERRA, INC ]
