STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
The Egress Interface is configured for the Clock Master: Clear Channel mode by
writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register.
ED[x] is sampled on the rising edge of the ECLK[x] output. When the the EDE bit
in the T1/E1 Serial Interface Configuration register is set to logic 0, then ED[x] is
sampled on the falling edge of ECLK[x], and the functional timing is described by
Figure 63 with the ECLK[x] signal inverted.
Figure 64: T1 Egress Interface Clock Slave: EFP Enabled mode
CECLK
CEFP
ED[x]
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
EFP[x]
Channel 24
Channel 1
Channel 2
Channel 24
Channel 1
Figure 65: E1 Egress Interface Clock Slave : EFP Enabled Mode
CECLK
CEFP
ED[x]
1
1 2 3 4 5 6 7 8 1
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
EFP[x]
Timeslot 31
Parity bit
(if enabled)
Timeslot 0
Timeslot 1
Timeslot 31
Timeslot 0
Parity bit
(if enabled)
The Egress Interface is configured for the Clock Slave: EFP Enabled mode by
writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register.
ED[x] is sampled on the active edge of CECLK and EFP[x] is updated on the
falling edge of CECLK.
In T1 mode, Figure 64, the CEMFP bit is written to logic 1 in the Master Egress
Slave Mode Serial Interface Configuration register, so that CEFP must pulse
once every 12 or 24 frames (for SF and ESF, respectively) on the first frame bit
of the multiframe. If parity checking is enabled, a parity bit should be inserted on
ED[x] in the first bit of each frame. The EFP[x] output will pulse high to mark the
F-bit of each frame in order to indicate frame alignment to an upstream device.
EFP[x] may be configured to mark superframe alignment instead by setting the
EMFP bit in the T1/E1 Serial Interface Configuration register.
PROPRIETARY AND CONFIDENTIAL
191
PMC [ PMC-SIERRA, INC ]
