STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 76: T1 Ingress Interface Clock Slave: External Signaling Mode
CICLK
CIFP
ID[x]
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A B C D A B C D A B C D
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8
A B C D A B C D
ISIG[x]
Channel 24
Channel 1
Channel 2
Channel 24
Channel 1
F-bit or Parity
F-bit or Parity
Figure 77: E1 Ingress Interface Clock Slave: External Signaling Mode
CICLK
CIFP
ID[x]
1 2 3 4 5 6 7 8 1
1 2 3 4 5 6 7 8
A B C D
1 2 3 4 5 6 7 8
A B C D
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A B C D
ISIG[x]
Timeslot 0
Timeslot 1
Timeslot 31
Timeslot 31
Timeslot 0
The Ingress Interface is programmed for Clock Slave mode by setting the
IMODE[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register. ID[x]
is timed to the active edge of CICLK, and is frame-aligned to CIFP. CIFP need
not be provided every frame. ID[x] and ISIG[x] may be configured to carry a
parity bit during the first bit of each frame. In External Signaling Mode, ISIG[x] is
active and is aligned as shown.
PROPRIETARY AND CONFIDENTIAL
197
PMC [ PMC-SIERRA, INC ]
