PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 05FH, 0DFH, 15FH, 1DFH, 25FH, 2DFH, 35FH, 3DFH: PMON LCV Count (MSB)
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
LCV[12]
LCV[11]
LCV[10]
LCV[9]
X
X
X
X
X
X
X
X
R
R
R
R
R
LCV[8]
LCV[12:0]:
The LCV[12:0] bits indicate the number of LCV error events that occurred during the previous
accumulation interval. An LCV event is defined as the occurrence of a Bipolar Violation or
Excessive Zeros. The counting of Excessive Zeros can be disabled by the BPV bit of the
Receive Line Interface Configuration #1 register.
The LCV count registers for a octant are updated by writing to the PMON LCV Count (LSB)
register. A write to this location loads count data located in the PMON into the internal
holding registers. Alternatively, the LCV count registers for the octant are updated by writing
to the Line Interface Interrupt Source #1 / PMON Update register. The data contained in the
holding registers can then be subsequently read by microprocessor accesses into the PMON
count register address space. The latching of count data, and subsequent resetting of the
counters, is synchronized to the internal event timing so that no events are missed.
The PMON is loaded with new count data within 3.5 recovered clock periods of the triggering
register write. With nominal line rates, the PMON registers should not be polled until
2.3 µsec have elapsed from the triggering register write.
When the OCTLIU is reset, the contents of the PMON count registers are unknown until the
first latching of performance data is performed.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
137
PMC [ PMC-SIERRA, INC ]
