PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 058H, 0D8H, 158H, 1D8H, 258H, 2D8H, 358H, 3D8H: PMON Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
INTE
X
X
X
X
X
0
R/W
R
XFER
0
Unused
X
This register contains status information indicating when counter data has been transferred into
the holding registers and indicating whether the holding registers have been overrun.
INTE:
The INTE bit controls the generation of a microprocessor interrupt when the transfer clock
has caused the counter values to be stored in the holding registers. A logic 1 bit in the INTE
position enables the generation of an interrupt via the INTB output; a logic 0 bit in the INTE
position disables the generation of an interrupt.
XFER:
The XFER bit indicates that a transfer of counter data has occurred. A logic 1 in this bit
position indicates that a latch request, initiated by writing to one of the counter register
locations or the Octant PMON Update register, was received and a transfer of the counter
values has occurred. A logic 0 indicates that no transfer has occurred. The XFER bit is
cleared (acknowledged) by reading this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
135
PMC [ PMC-SIERRA, INC ]
