PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H:
PRBS Checker Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R
SYNCE
BEE
0
0
XFERE
SYNCV
SYNCI
BEI
0
X
X
X
X
X
R
R
R
XFERI
Unused
SYNCE:
The SYNCE bit enables the generation of an interrupt when the PRBS checker changes
synchronization state. When SYNCE is set to logic 1, the interrupt is enabled.
BEE:
The BEE bit enables the generation of an interrupt when a bit error is detected in the receive
data. When BEE is set to logic 1, the interrupt is enabled.
XFERE:
The XFERE bit enables the generation of an interrupt when an accumulation interval is
completed and new values are stored in the error counter holding registers. When XFERE is
set to logic 1, the interrupt is enabled.
SYNCV:
The SYNCV bit indicates the synchronization state of the PRBS checker. When SYNCV is a
logic 1 the PRBS checker is synchronized (the PRBS checker has observed at least 32
consecutive error free bit periods). When SYNCV is a logic 0, the PRBS checker is out of
sync (the PRBS checker has detected 6 or more bit errors in a 64 bit period window).
SYNCI:
The SYNCI bit indicates that the detector has changed synchronization state since the last
time this register was read. If SYNCI is logic 1, the pattern detector has gained or lost
synchronization at least once. SYNCI is set to logic 0 when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
140
PMC [ PMC-SIERRA, INC ]
