PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 056H, 0D6H, 156H, 1D6H, 256H, 2D6H, 356H, 3D6H: CDRC Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
LCVI
LOSI
X
X
X
X
X
X
X
X
LCSDI
ZNDI
Unused
Unused
Unused
LOSV
R
The ZNDI, LCSDI, LOSI and LCVI (bits 4 to 7) of this register indicate which of the status events
have occurred since the last time this register was read. A logic 1 in any of these bit positions
indicates that the corresponding event was detected.
Bits ZNDI, LCSDI, LOSI and LCVI are cleared to logic 0 by reading this register.
LOSV:
The LOSV bit reflects the status of the LOS alarm.
ZNDI:
The consecutive zeros detection interrupt (ZNDI) indicates that N consecutive spaces have
occurred, where N is four for E1 and eight for T1. This bit can be used to detect an AMI
coded signal.
LCSDI:
The line code signature detection interrupt (LCSDI) indicates that a valid line code signature
has occurred. In T1 mode, the B8ZS signature is defined as 000+-0-+ if the previous impulse
is positive, or 000-+0+- if it is negative. In E1 mode, a valid HDB3 signature is defined as a
bipolar violation preceded by two zeros. This bit can be used to detect an HDB3 coded signal
in E1 mode and B8ZS coded signal in T1.
LOSI:
The LOSI bit is set to a logic 1 when the LOSV bit changes state.
LCVI:
The line code violation interrupt (LCVI) indicates a series of marks and spaces has occurred
in contradiction to the defined line code (AMI, B8ZS or HDB3).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
133
PMC [ PMC-SIERRA, INC ]
