PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 057H, 0D7H, 157H, 1D7H, 257H, 2D7H, 357H, 3D7H:
CDRC Alternate Loss of Signal Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R
ALTLOSE
ALTLOSI
Unused
Unused
Unused
Unused
Unused
ALTLOSV
0
X
X
X
X
X
X
X
R
The alternate loss of signal status provides a more stringent criteria for the deassertion of the
alarm than the LOS indication in the CDRC Interrupt Status register.
ALTLOSE:
If the ALTLOSE bit is a logic 1, the INTB output is asserted low when the ALTLOSV status bit
changes state.
ALTLOSI:
The ALTLOSI bit is set high when the ALTLOSV status bit changes state. It is cleared when
this register is read.
ALTLOSV:
The ALTLOSV bit is asserted upon the absence of marks for the threshold of bit periods
specified by the LOS[1:0] register bits. The ALTLOSV bit is deasserted only after pulse
density requirements have been met. In T1 mode, there must be N ones in each and every
time window of 8(N+1) data bits (where N can equal 1 through 23). In E1 mode, ALTLOSV is
deasserted only after 255 bit periods during which no sequence of four zeros has been
received.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
134
PMC [ PMC-SIERRA, INC ]
