PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H:
PRBS Generator/Checker Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
QRSS
X
X
0
X
0
0
1
0
R/W
Unused
TINV
R/W
R/W
R/W
R/W
RINV
AUTOSYNC
MANSYNC
QRSS:
The quasi-random signal source (QRSS) bit enables the zero suppression feature required
when generating a QRSS sequence. When QRSS is a logic 1, a one is forced in the
generated PRBS stream when the following 14 bit positions are all zeros. When QRSS is a
logic 0, the zero suppression feature is disabled.
Note that in order to generate the AT&T TR 62411 QRSS sequence, or the 220-1 sequence as
specified in ITU-T O.151, the PATSEL[1:0] field in the PRBS Pattern Select Register must be
set to “01” and QRSS set to 1.
TINV:
The TINV bit controls the logical inversion of the generated data stream. When TINV is a
logic 1, the data is inverted. When TINV is a logic 0, the data is not inverted.
RINV:
The RINV bit controls the logical inversion of the received stream before processing. When
RINV is a logic 1, the received data is inverted before being processed by the pattern
detector. When RINV is a logic 0, the data is not inverted
AUTOSYNC:
The AUTOSYNC bit enables the automatic resynchronization of the pattern detector. The
automatic resynchronization is activated when 10 or more bit errors are detected in a fixed
48-bit window. When AUTOSYNC is a logic 1, the auto resync feature is enabled. When
AUTOSYNC is a logic 0, the auto sync feature is disabled, and pattern resynchronization is
accomplished using the MANSYNC bit.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
138
PMC [ PMC-SIERRA, INC ]
