PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
DCR:
The disable clock recovery (DCR) bit is logically "ORed" with the DCR input
pin. DCR enables the sliced positive and negative pulses from the analog
receive slicer to be visible on the SDP[X] and SDN[X] outputs. When DCR is
set to logic 1, the SDP[X] and SDN[X] outputs are enabled. When DCR is set
to logic 0, either the RDP[X] and RDN[X] or the RDD[X] and RLCV[X] outputs
are enabled depending on the setting of the RDUAL bit in the Receive
Configuration register (000H, 040H, 080H, and 0C0H). Note that the DCR bit
takes precedence over the RDUAL bit.
ALGSEL:
The Algorithm Select (ALGSEL) bit specifies the algorithm used by the DPLL
for clock and data recovery.The choice of algorithm determines the high
frequency input jitter tolerance of the CDRC. When ALGSEL is set to logic 1,
the CDRC jitter tolerance is increased to approach 0.5UIpp for jitter
frequencies above 20KHz. When ALGSEL is set to logic 0, the jitter tolerance
is increased for frequencies below 20KHz (i.e. the tolerance is improved by
20% over that of ALGSEL=1 at these frequencies), but the tolerance
approaches 0.4UIpp at the higher frequencies.
O162:
When the E1 format is selected and the AMI bit is logic 0, the
Recommendation O.162 compatibility select bit (O162) allows selection
between two line code definitions:
1. If O162 is a logic 0, a line code violation is indicated if the serial stream
does not match the verbatim HDB3 definition given in Recommendation
G.703. A bipolar violation that is not part of an HDB3 signature or a bipolar
violation in an HDB3 signature that is the same polarity as the last bipolar
violation results in a line code violation indication.
2. If O162 is a logic 1, a line code violation is indicated by a LCV output
pulse if a bipolar violation is of the same polarity as the last bipolar violation,
as per Recommendation O.162.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
75
PMC [ PMC-SIERRA, INC ]
