PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Register 014H, 054H, 094H, and 0D4H: LCV_PMON Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
INTE
X
X
X
X
X
0
R/W
R
INT
X
X
R
OVR
INTE:
The INTE bit controls the generation of a microprocessor interrupt when the
transfer clock has caused the counter values to be stored in the holding
registers. A logic 1 bit in the INTE position enables the generation of an
interrupt. A logic 0 bit in the INTE position disables the generation of an
interrupt.
INT:
The INT bit is the current status of the interrupt signal. A logic 1 in this bit
position indicates that a transfer has occurred. A logic 0 indicates that no
transfer has occurred. The interrupt is cleared (acknowledged) by reading
this register.
OVR:
The OVR bit is the overrun status of the holding registers. A logic 1 in this bit
position indicates that a previous interrupt has not been acknowledged before
the next transfer clock has been issued and that the contents of the holding
registers have been overwritten. A logic 0 indicates that no overrun has
occurred.The OVR bit is cleared by reading this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
78
PMC [ PMC-SIERRA, INC ]
