PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Registers 012H, 052H, 092H and 0D2H: CDRC Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
LCVI
LOSI
X
X
X
X
X
X
X
X
LCSDI
EXZI
Unused
Unused
Unused
LOS
R
The bit positions LCVI, LOSI, LCSDI and EXZI of this register indicate which of
the status events generated an interrupt. A logic 1 in these bit positions indicate
that the corresponding event was detected; a logic 0 in these bit positions
indicate that no corresponding event has been detected. The bit positions LCVI,
LCSDI and EXZI are set on the assertion of a line code violation, a line code
signature detection, and excessive zeros detection, respectively. LOSI is set on
a change of state of the LOS alarm. Bits LCVI, LOSI, LCSDI and EXZI are
cleared by reading this register.The current state of the LOS alarm can be
determined by reading bit 0 of this register.
Note:
In the CDRC, excess zeros is defined as a string greater than: 3 consecutive
zeros for E1 data, or 7 consecutive zeros for T1 data.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
77
PMC [ PMC-SIERRA, INC ]
