PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Registers 01AH-01BH, 05AH-05BH, 09AH-09BH, 0DAH-0DBH: Latching LCV
Performance Data
The LCV Performance Data registers for one of the four interfaces on the QDSX
are updated as a group by writing to any of the LCV_PMON count registers
(addresses 01AH-01BH, 05AH-05BH, 09AH-09BH, 0DAH-0DBH). A write to any
of these locations loads performance data located in the LCV_PMON block of
that quadrant into the internal holding registers.The data contained in the
holding registers can then be subsequently read by microprocessor accesses of
the LCV_PMON LCV Count registers.The latching of count data, and
subsequent resetting of the counters, is synchronized to the internal event timing
so that no events are missed. NOTE: it is necessary to write to one, and only
one, count register address to latch all the count data register values into the
holding registers and to reset all the counters of the particular quadrant for each
polling cycle.
Alternately, one may write to the Global Monitoring Update register (009H) to
transfer the contents of all four LCV_PMON counters and the PRSM counters.
The transfer in progress (TIP) bit in register 007H is polled to determine when
the transfer is complete.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
79
PMC [ PMC-SIERRA, INC ]
