PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Register 00AH, 04AH, 08AH, and 0CAH:TOPS ClockTiming Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
X
X
X
X
X
0
Unused
Unused
Unused
R/W
R/W
R/W
FIFOBYP
PLLREF[1]
PLLREF[0]
0
0
This register is used to configure the timing options for the corresponding QDSX
quadrant. Figure 12 illustrates the different timing configurations.
FIFOBYP:
The FIFOBYP bit enables the transmit input signals to DJAT to be bypassed
around the FIFO to the outputs. When FIFOBYP is set to logic 1, the inputs
to DJAT are routed around the FIFO to the outputs. When FIFOBYP is set to
logic 0, the transmit data passes through the DJAT FIFO. When the DJATTX
bit (registers 002H, 042H, 082H, and 0C2H) is set to logic 0, the FIFO is
automatically bypassed on the transmit path. Whenever the FIFO is not
active in the transmit path, the system 8X clock (presented on CLK08X) must
be synchronous to TCLKI[X], and line loopback cannot be used. Refer to the
Operations section for more details on using the QDSX without the DJAT
enabled in the transmit path.
PLLREF[1:0]:
The PLLREF[1:0] bits select the source of the Digital Jitter Attenuator phase
locked loop reference signal as follows:
PLLREF[1]
PLLREF[0] Transmit Reference Source
0
0
0
1
TCLKI[X] input.
Clock recovered from the RXTIP[X] and
RXRING[X] inputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
71
PMC [ PMC-SIERRA, INC ]
