PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PLLREF[1]
PLLREF[0] Transmit Reference Source
1
0
XCLK input divided by 24. XSEL[1] must be set
to 0 if this option is selected. (register 009H)
1
1
Reserved. Not to be used.
Figure 17
-Timing Options
1
DJAT
FIFO
FIFO input
data clock
1
0
0
DJATTX
FIFOBP
DJATTX
"AND"
XPLS data
clock
XPLS Reference
8X Clock
not(LINELB)
0
1
1
XSEL[1]
0
1
1
XPLS
*setting LINELB automatically
selects PLLREF[1:0] = 01B.
1x "Jitter
Attenuated"
Clock
TXTIP[x],
TXRING[x]
00
TCLKI[x]
DJAT
PLL
FIFOBP
"OR"
XSEL[1]
Smooth 8X Clock
0
01
1
PLLREF[1:0]
24x reference clock for
jitter attenuation
10
0
1
CLKO8X
CLKO1X
÷ 8
XCLK
(24X, 8X)
XSEL[0]
"OR"
XSEL[1]
÷ 3
0x
10
8x "High-speed" clock
XSEL[1:0]
CDRC
0
RCLKO[x]
1
DJATTX
"OR"
XSEL[1]
Note:
The CLKO8X and CLKO1X outputs are generated from the first quadrant of the
device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
72
PMC [ PMC-SIERRA, INC ]
