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PEX8532-BB25BI 参数 Datasheet PDF下载

PEX8532-BB25BI图片预览
型号: PEX8532-BB25BI
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PBGA680, 35 X 35 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-680]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 512 页 / 4374 K
品牌: PLX [ PLX TECHNOLOGY ]
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February, 2007  
PEX 8532 Port Register Configuration and Map  
11.3  
PEX 8532 Port Register Configuration and Map  
The PEX 8532 port registers are configured similarly – not all the same. Port 0 of Station 0 and Port 8 of  
Station 1 include more device-specific registers than the other station ports. The registers for these ports  
contain setup and control information specific to the station. Also, Port 0 of Station 0 contains registers  
used to set up and control the switch, and serial EEPROM interface logic and control.  
The port register map is defined in Table 11-2. (Refer to Appendix A, “Serial EEPROM Memory Map,”  
for a detailed description of this register map.)  
Table 11-2. PEX 8532 Port Register Configuration and Map  
Station 0,  
Station 1,  
Port 8  
Station 0, Ports 1, 2, 3  
Station 1, Ports 9, 10, 11  
Register Types  
Port 0  
Configuration Header Registers  
00h - 3Ch  
40h - 44h  
00h - 3Ch  
40h - 44h  
00h - 3Ch  
40h - 44h  
Power Management Capability Registers  
Message Signaled Interrupt Capability Registers  
PCI Express Capability Registers  
Device Serial Number Extended Capability Registers  
Power Budgeting Extended Capability Registers  
Virtual Channel Extended Capability Registers  
ECC Check Disable  
48h - 64h  
48h - 64h  
48h - 64h  
68h - 8Ch  
68h - 8Ch  
100h - 108h  
138h - 144h  
148h - 1C4h  
1C8h  
68h - 8Ch  
100h - 108h  
138h - 144h  
148h - 1C4h  
1C8h  
100h - 108h  
138h - 144h  
148h - 1C4h  
Device-Specific Error  
1CCh - 1D0h  
1D4h - 1DCh  
1CCh - 1D0h  
1D4h - 1D8h  
Debug  
1E0h - 1ECh,  
1F8h - 1FCh  
Power Management, Hot Plug, and Miscellaneous Control  
1E0h - 1FCh  
1E0h - 1ECh, 1F8h - 1FCh  
Physical Layer (all except for Serial EEPROM-related)  
Serial EEPROM  
200h - 25Ch  
260h - 264h  
2C8h - 2F4h  
308h - 31Ch  
348h - 404h  
660h - 73Ch  
680h - 6ACh  
6C0h - 71Ch  
200h - 25Ch  
Bus Number CAM Station 0, Station 1  
I/O CAM Station 0, Station 1  
2C8h - 2F4h  
308h - 31Ch  
348h - 404h  
660h - 73Ch  
680h - 6ACh  
6C0h - 71Ch  
AMCAM Memory Base and Limit  
Ingress Control Registers  
I/O CAM Upper Station 0, Station 1  
Station 0 BAR, Station 1 BAR  
740h - 79Ch  
840h - 9ECh  
740h - 79Ch  
840h - 9ECh  
Virtual Channel Station 0, Station 1  
740h  
Ingress Credit Handler (INCH) Registers  
Ingress One-Bit ECC Error Count Register  
9F0h - B7Ch  
BE8h  
9F0h- B7Ch  
BE8h  
A00h - B7Ch  
Relaxed Completion Ordering (Ingress) Register –  
Silicon Revisions BA/BB/BC Only  
BECh  
BECh  
Relaxed Ordering Mode (Ingress) Register  
BF0h - BFCh  
C00h - C08h  
FB4h - FFCh  
BF0h - BFCh  
C00h - C08h  
FB4h - FFCh  
Internal Credit Handler (ITCH) VC&T Threshold Registers  
Advanced Error Reporting Capability Registers  
FB4h - FFCh  
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book  
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6  
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