February, 2007
Using Base Address Registers (BARs) to Access Registers
7.3.2.1
Transparent Mode Registers
The formula to locate register addresses for Transparent ports is as follows:
BAR0 + (port * 1000h) + register_offset
For example, to hit the Memory Base and Limit Address (offset 20h) for each port, refer to Table 7-1
and Figure 7-4. Table 7-1 defines how the registers in each port can be reached. All registers for all ports
sit in the same BAR. Using the formula 1000h x Port Number provides the start address for the first
register in a port. Figure 7-4 provides a graphical view of the BAR Memory space.
Table 7-1. PEX 8532 Memory-Mapped Register Access
Register
Location Address
0100_0020h
0100_1020h
0100_2020h
0100_3020h
0100_8020h
0100_9020h
0100_A020h
0100_B020h
Port 0 Base and Limit
Port 1 Base and Limit
Port 2 Base and Limit
Port 3 Base and Limit
Port 8 Base and Limit
Port 9 Base and Limit
Port 10 Base and Limit
Port 11 Base and Limit
Note: For a complete listing of Memory-Mapped Register accesses, refer to Section A.1,
“Serial EEPROM Memory Map.”
Figure 7-4. Using Memory-Mapped Access for PEX 8532 in Transparent Mode
PEX 8532
0 KB
BAR0 = 0100_0000h
Port 0
4 KB
Base and Limit for Port 0 =
Port 1
0100_0020h
8 KB
Port 2
12 KB
Port 3
16 KB
Reserved
Base and Limit for Port 8 =
32 KB
Port 8
0100_8020h
36 KB
Port 9
40 KB
Port 10
44 KB
Port 11
48 KB
64 KB
68 KB
Reserved
72 KB
128 KB
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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