Reset and Initialization
PLX Technology, Inc.
5.3.12
Reset and Clock Initialization Timing
Table 5-3. Reset and Clock Initialization Timing
Symbol
td1
Description
Typical Delay
100 µs
REF Clock stable to PEX_Reset release time
PEX_Reset release to PLL Clock Stable and Reset de-bounce
Clock and Reset Stable to PLL Lock
td2
1.32 ms
125 µs
td3
td4
PLL Lock to BIST Done time, which causes Core Reset release
Core Reset release to SerDes Resets active delay
SerDes Reset active time
4.5 ms
td5
10 µs
td6
60 µs
td7
Serial EEPROM load time
12.6 ms
Figure 5-3. Reset and Clock Initialization Timing
Clock Stable
PEX_REFCLK
100 MHz
td1
PEX_PERST#
Clock Stable
td2
PLL/SCLK
250 MHz
td3
PLL_LOCK
td4
BIST_DONE
CORE_RESET#
SerDes_RESET
td6
td5
Inactive
Inactive
Active
Clock Stable
SerDes_
CLOCK
td7
Serial EEPROM
LOAD
80
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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