欢迎访问ic37.com |
会员登录 免费注册
发布采购

PEX8532-BB25BI 参数 Datasheet PDF下载

PEX8532-BB25BI图片预览
型号: PEX8532-BB25BI
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PBGA680, 35 X 35 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-680]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 512 页 / 4374 K
品牌: PLX [ PLX TECHNOLOGY ]
 浏览型号PEX8532-BB25BI的Datasheet PDF文件第102页浏览型号PEX8532-BB25BI的Datasheet PDF文件第103页浏览型号PEX8532-BB25BI的Datasheet PDF文件第104页浏览型号PEX8532-BB25BI的Datasheet PDF文件第105页浏览型号PEX8532-BB25BI的Datasheet PDF文件第107页浏览型号PEX8532-BB25BI的Datasheet PDF文件第108页浏览型号PEX8532-BB25BI的Datasheet PDF文件第109页浏览型号PEX8532-BB25BI的Datasheet PDF文件第110页  
Interrupts  
PLX Technology, Inc.  
6.3  
Message Signaled Interrupt (MSI) Support  
One of the interrupt schemes supported by the PEX 8532 is the MSI mechanism, which is required for  
PCI Express devices. The MSI method uses Memory Write transactions to deliver interrupts. MSIs are  
edge-triggered interrupts.  
Note: MSI and INTx are mutually exclusive. These interrupt mechanisms cannot  
be simultaneously enabled.  
6.3.1  
MSI Operation  
At configuration time, system software traverses the function Capability list. If a Capability ID of 05h is  
found, the function implements MSI. System software reads the MSI Capability Structure registers to  
determine function capabilities.  
The PEX 8532 supports only one message for MSI; therefore, the Message Control register Multiple  
Message Enable and Multiple Message Capable fields (offset 48h[22:20, 19:17], respectively) are  
always cleared to 000b.  
The Message Control register MSI 64-Bit Address Capable bit is enabled (offset 48h[23]=1),  
by default.  
System software initializes the MSI Capability Structure registers with a system-specified message.  
If the MSI function is enabled, after an Interrupt event occurs, the Interrupt Generation module  
generates a DWord Memory Write to the address specified by the Message Address[31:0] register  
(offset 4Ch) contents. Data written is the contents of the Message Data register (offset 54h) lower two  
bytes and zeros (0) in the upper two bytes. Because the Message Control register Multiple Message  
Enable field (offset 48h[22:20]) field is always cleared to 000b, the Interrupt Generation module is not  
allowed to change the low-order bits of Message data.  
When the Hot Plug and/or device-specific error events that caused the interrupt are serviced, the device  
can generate a new MSI Memory Write as a result of new events.  
6.3.2  
MSI Capability Registers  
MSI Capability registers are described in Section 11.8, “Message Signaled Interrupt Capability  
Registers.”  
84  
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book  
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6  
 复制成功!