Interrupts
PLX Technology, Inc.
6.2
INTx Emulation Support
The PEX 8532 supports PCI INTx emulation, to signal interrupts to the System Interrupt Controller.
This mechanism is compatible with existing PCI software. PCI INTx emulation virtualizes PCI physical
Interrupt signals, by using the in-band signaling mechanism.
PCI Interrupt registers (the Interrupt registers defined in the PCI r2.3) are supported. The PCI r2.3
Command register Interrupt Disable and Status register Interrupt Status bits are also supported
(offset 04h[10, 19], respectively).
Although the PCI Express Base r1.0a provides INTA#, INTB#, INTC#, and INTD# for INTx signaling,
the PEX 8532 uses only INTA# for internal Interrupt message generation, because it is a single-function
device. However, incoming messages from downstream devices can be of INTA#, INTB#, INTC#, or
INTD# type. Internally generated INTA# messages from the downstream port are also remapped and
collapsed at the upstream port, according to the downstream port’s Device Number, with its own Device
Number and Received Device Number from the downstream device. When an interrupt is requested, the
Status register Interrupt Status bit is set. If INTx interrupts are enabled [Command register Interrupt
Disable and Message Control register MSI Enable bits (offsets 04h[10] and 48h[16], respectively) are
cleared to 0], an Assert_INTx message is generated and transmitted upstream to indicate the port
interrupt status. For each interrupt event, there is a corresponding Mask bit. The Interrupt request can be
generated only when the Mask bit is not set. Software reads and clears the event and Interrupt Status bit
after servicing the interrupt.
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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