Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
MVCL_7
MVCR_7
MVCL_6
MVCR_6
MVCL_5
MVCR_5
MVCL_4
MVCR_4
MVCL_3
MVCR_3
MVCL_2
MVCR_2
MVCL_1
MVCR_1
MVCL_0
VOLUME (dB)
MVCR_0
1
1
:
1
1
:
0
0
:
1
1
:
0
1
:
1
0
:
0
0
:
0
0
:
−54
−56
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
−66
−69
−72
−78
−∞
Table 39 Register address 11H
BIT
15
14
13
12
11
10
9
8
Symbol
Default
VC2_7
1
VC2_6
1
VC2_5
1
VC2_4
1
VC2_3
1
VC2_2
1
VC2_1
VC2_0
1
1
BIT
7
6
5
4
3
2
1
0
Symbol
Default
VC1_7
0
VC1_6
0
VC1_5
0
VC1_4
0
VC1_3
0
VC1_2
0
VC1_1
0
VC1_0
0
Table 40 Description of register bits (address 11H)
BIT SYMBOL
DESCRIPTION
15 to 8 VC2_[7:0]
Mixer volume setting channel 2. Value to program channel 2 mixer volume attenuation. The
range is 0 dB to −72 dB and ∞ dB (see Table 41).
7 to 0 VC1_[7:0]
Mixer volume setting channel 1. Value to program channel 1 mixer volume attenuation. The
range is 0 dB to −72 dB and ∞ dB (see Table 41).
Table 41 Mixer volume setting channel 1 and 2
VC2_7 VC2_6 VC2_5 VC2_4 VC2_3 VC2_2 VC2_1 VC2_0
VC1_7 VC1_6 VC1_5 VC1_4 VC1_3 VC1_2 VC1_1 VC1_0
VOLUME (dB)
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
1
:
0
0
1
1
0
:
0
1
0
1
0
:
0
−0.25
−0.5
−0.75
−1
:
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
−45
−45.25
−45.5
−45.75
−46
2003 Apr 10
46
NXP [ NXP ]
