Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
Table 35 ADC power control
PON_ADC_BIAS
PON_ADCR
PON_ADCL
DESCRIPTION
no power on both ADCs
0
1
1
1
1
X
0
1
0
1
X
0
0
1
1
no power on both ADCs
only power on right channel ADC
only power on left channel ADC
power on both ADCs
12.2.2 INTERPOLATOR
Table 36 Register address 10H
BIT
15
MVCL_7
0
14
MVCL_6
0
13
12
11
MVCL_3
0
10
MVCL_2
0
9
MVCL_1
0
8
MVCL_0
0
Symbol
Default
MVCL_5
0
MVCL_4
0
BIT
7
MVCR_7
0
6
MVCR_6
0
5
MVCR_5
0
4
MVCR_4
0
3
MVCR_3
0
2
MVCR_2
0
1
MVCR_1
0
0
MVCR_0
0
Symbol
Default
Table 37 Description of register bits (address 10H)
BIT SYMBOL
15 to 8 MVCL_[7:0]
DESCRIPTION
Master volume setting left channel. Value to program the left channel master volume
attenuation. The range is 0 dB to −78 dB and ∞ dB (see Table 38).
7 to 0 MVCR_[7:0] Master volume setting right channel. Value to program the right channel master volume
attenuation. The range is 0 dB to −78 dB and ∞ dB (see Table 38).
Table 38 Master volume setting left and right channel
MVCL_7
MVCR_7
MVCL_6
MVCR_6
MVCL_5
MVCR_5
MVCL_4
MVCR_4
MVCL_3
MVCR_3
MVCL_2
MVCR_2
MVCL_1
MVCR_1
MVCL_0
MVCR_0
VOLUME (dB)
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
1
:
0
0
1
1
0
:
0
1
0
1
0
:
0
−0.25
−0.5
−0.75
−1
:
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
−51
−51.25
−51.5
−51.75
−52
2003 Apr 10
45
NXP [ NXP ]
