Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
MODE
FEATURES
SCHEMATIC
7
Data path:
• Input SPDIF to output DAC
• Input ADC to outputs SPDIF or I2S.
Features:
• Crystal oscillator generates the clocks
SPDIF LOCK
MUTE
for outputs SPDIF and I2S
XTAL
PLL
• PLL locks onto the SPDIF input signal
• WS of I2S output is master
ADC
DAC
• Microcontroller mode:
SPDIF OUT
SPDIF IN
– Decimator features can be used
– DAC sound features can be used
2
2
I S OUTPUT
I S master
MGU843
– SPDIF input channel status bits
(two times 40 bits) can be read
– SPDIF output channel status bits
(two times 40 bits) setting.
8
Data path:
• Input ADC to outputs SPDIF or I2S
• Input I2S to output DAC.
Features:
2
I
S LOCK
XTAL
PLL
• Possibility to process input ADC, via
I2S-bus using an external DSP and
then to output DAC
MUTE
ADC
DAC
• Crystal oscillator generates the clocks
for outputs SPDIF and I2S
SPDIF OUT
2
• WSI is slave
2
I S INPUT
I S OUTPUT
• WSO master
2
2
I S slave
I S master
• Microcontroller mode:
– Decimator features can be used
– DAC sound features can be used
EXTERNAL DSP
(e.g. Sample Rate Convertor)
(SAA7715)
MGU844
– SPDIF output channel status bits
(two times 40 bits) setting.
2003 Apr 10
24
NXP [ NXP ]
