Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
8.4
Microcontroller mode applications
In Table 13, the encoding of bits MODE[3:0] in the microcontroller mode is given.
Table 13 Microcontroller mode applications
MODE BITS
CLOCK(1)
PLL
LOCKS
ON
INPUT
I2S-BUS
INPUT
SLAVE
I2S-BUS
OUTPUT
MASTER
MODE
SPDIF
INPUT
SPDIF
OUTPUT
MODE[3:0]
ADC
DAC
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL
−
PLL
PLL
PLL
xtal
xtal
xtal
PLL
xtal
xtal
xtal
xtal
−
PLL
PLL
-
PLL
−
SPDIF
I2S
−
PLL
PLL
−
2
PLL
−
PLL
xtal
xtal
xtal
xtal
xtal
xtal
xtal
PLL
PLL
PLL
xtal
xtal
xtal
xtal
xtal
xtal
PLL
PLL
SPDIF
−
3
−
4
−
xtal
xtal
xtal
PLL
−
−
5
−
xtal
−
I2S
6
−
PLL
7
PLL
−
PLL
SPDIF
I2S
8
PLL
PLL
xtal
xtal
9
PLL
PLL
xtal
SPDIF
SPDIF
10
11
12
13
14
15
PLL
not used
PLL
PLL
PLL
−
xtal
PLL
PLL
xtal
xtal
PLL
PLL
PLL
PLL
xtal
xtal
PLL
SPDIF
SPDIF
I2S
PLL
PLL
not used
Note
1. In column clock means:
xtal: the clock is based on the crystal oscillator; PLL: the clock is based on the PLL.
2003 Apr 10
27
NXP [ NXP ]
