Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
In the microcontroller mode, more features are available. The application modes are given in Table 14. Some modes are
the same in terms of data path as for the static mode. These modes are already explained in Section 8.2. Some modes
are combined into one mode (like modes 4 and 5).
Table 14 Overview of microcontroller modes
MODE
FEATURE
See static mode
SCHEMATIC
0
1
2
See static mode
Data path:
• Inputs ADC, I2S and SPDIF to outputs
DAC, I2S or SPDIF.
SPDIF LOCK
PLL
Features:
ADC
MUTE
• All clocks are related to the SPDIF
clock
DAC
• I2S input and output have master BCK
SPDIF IN
and WS
SPDIF OUT
• SPDIF input channel status bits (two
times 40) can be read
SPDIF
OUT
• Output SPDIF supported but the timing
not according to level II: depends on
I2S-bus clock
2
I S OUTPUT
2
I S INPUT
2
2
• Output SPDIFOUT loop through can
be selected with independent SPDIF
input channel select.
I S slave
I S master
EXTERNAL DSP
(e.g. equalizing, spatializing)
(SAA7715)
MGU847
3
See static mode
4 + 5 Data path:
• Inputs ADC and I2S to outputs DAC,
I2S or SPDIF.
XTAL
Features:
ADC
MUTE
• Mode 4 and 5 are combined in
microcontroller mode
DAC
• Crystal oscillator generates the clocks
• I2S input and output have master BCK
and WS
SPDIF OUT
• SPDIF output channel status bits (two
times 40) setting.
2
2
I S INPUT
I S OUTPUT
2
2
I S slave
I S master
EXTERNAL DSP
(e.g. equalizing, spatializing)
(SAA7715)
MGU848
2003 Apr 10
28
NXP [ NXP ]
