Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 70 Horizontal offset values for the field memory mode
RATIO
OFFSET
1
2
4
8
0CH
0CH
16H
2EH
7.12.5 HPS PROGRAMMING REGISTER
Table 71 HPS control register
OFFSET
NAME
BIT
TYPE
DESCRIPTION
(HEX)
5C
HPSdatasel 31 and 30 RW source select for HPS video data:
00: input video stream for HPS is taken from Port_A
01 input video stream for HPS is taken from Port_B
10: Y-byte from Port_B, C-byte from Port_A (CREF must provide at
Port_A)
11: Y-byte from Port_A, C-byte from Port_B (CREF must provide at
Port_B)
Mirror
29
28
RW left-right flip (mirroring), e.g. for vanity picture:
0: regular processing
1: left-right flip, accessible only if XT (number of pixel after horizontal
prescaling) is less than 384 pixels
HPSsyncsel
RW source select for HPS sync-signals:
0: take Ha, Va, Fa, LLC_A as selected in Table 66
1: take Hb, Vb, Fb, LLC_B, as selected in Table 66
RW reserved
−
27 to 24
23 to 12
HYO
RW vertical offset (start line) of HPS operation, counted in horizontal
source/input events, after selected vertical sync edge
−
11 to 0
RW reserved
1998 Apr 09
89
NXP [ NXP ]
