Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 79 HPS, horizontal prescaler
OFFSET
(HEX)
NAME
BIT
TYP.
DESCRIPTION
68
−
31 and 30
29 to 27
−
reserved
DCGX
RW
DC gain control of X prescaler (see Table 57): depending on the
number of active coefficients ‘2’ in the accumulation sequence and
the sequence length, the output amplitude gain has to be set to as
given in Table 80.
−
26 to 24
23 to 18
−
reserved
XPSC
RW
prescaling factor of the X PreSCaler: defines accumulation
sequence length and subsampling factor of the input data stream:
XPSC = TRUNC (NIP/NOP − 1)
NOP = number of prescaler output pixel
NIP = number of qualified scaler input pixel.
XACM
17
RW
X (horizontal) prescaler Accumulation Mode of accumulating
FIR:
0: accumulating operates overlapping
1: non overlapping accumulation (must be set to bypass the
prescaler).
−
16
−
reserved
CXY
15 to 8
RW
Coefficient select for X prescaler (luminance component Y):
for DC gain compensation of prescaler the accumulated pixels can
be weighted by ‘1’ or ‘2’. CXYi defines a sequence of 8 bits, which
control the coefficients:
CXYi = 0: pixel weighted by ‘1’
CXYi = 1: pixel weighted by ‘2’
CXUV
7 to 0
RW
Coefficient select for X prescaler (colour difference signals
UV): for DC gain compensation of prescaler the accumulated
pixels can be weighted by ‘1’ or ‘2’. CXUVi defines a sequence of
8 bits, which control the coefficients:
CXUVi = 0: pixel weighted by ‘1’
CXUVi = 1: pixel weighted by ‘2’
Table 80 Selection of output gain
DCGX2
DCGX1
DCGX0
GAIN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
⁄
2
1
⁄
4
1
⁄
8
1
⁄
2
1
⁄
4
1
⁄
8
1
⁄
16
1998 Apr 09
93
NXP [ NXP ]
