Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 73 HPS, vertical scale and gain
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
64
PFY
31 to 28
RW
prefilter selection for luminance component Y:
H(z) = H1(z) × H2(z) × H3(z)
H1, H3 = 1 + z−1
H2 = 1 + A × z−1 + z−2
see Table 74
PFUV
27 to 24
RW
prefilter selection for colour difference signals UV:
H(z) = H1(z) × H2(z) × H3(z)
H1 = 1 + z−1
H2 = 1 + A × z−1 + z−2
H3 = 1 + z−2
see Table 75
−
23 to 19
18 to 16
−
reserved
DCGY
RW
DC gain control of Y scaler:
Dependent on active coefficients and the sequence length, the
amplitude gain has to be renormalized.
Gain factor = 2 (DCGY + 1); see Table 76. The resulting factor is a
function of CYi and DCGY. The resulting weight factor = 0 for
CYAi = CYBi = 0 or CYAi = CYBi = 1 or DCGY >5 otherwise
weight = weighting factor/gain factor; see Table 77.
CYA
CYB
15 to 8
7 to 0
RW
RW
Coefficient select for Y (vertical) processing in accumulation mode.
For improvement of vertical filtering the accumulated lines can be
weighted. Weighting factor = 2(2 × CYBi + CYAi − 1); see Table 78.
Table 74 Prefilter selection for luminance component Y
PFY1
PFY0
PFY1
PFY0
H1
H2
H3
A
X
X
X
0
0
1
1
X
X
X
0
1
0
1
0
0
1
1
1
1
1
0
1
0
1
1
1
1
bypass
active
active
active
active
active
active
bypass
bypass
bypass
active
bypass
bypass
active
active
bypass
active
active
X
X
X
2
15
bypass
bypass
active
⁄
⁄
⁄
16
7
3
8
4
1998 Apr 09
91
NXP [ NXP ]
