Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.12.2 VIDEO DATA STREAM HANDLING AT PORT D1_A
Table 67 Video data stream handling at port D1_A
OFFSET
NAME
BIT
TYPE
DESCRIPTION
(HEX)
54
VID_A
31 and 30
RW
Video data Port_A and PXQ_A select (PXQ goes always with data):
00: input, i.e. 3-state
01: reserved
10: output data stream is Y8C from BRS
11: output data stream is Y8C from HPS
Y8C codes, if output Y8C only:
0: no SAV and EAV data in the video data output-stream
1: with SAV and EAV
Y8C_A
29
RW
−
28 and 27
26
−
reserved
PFID_A
RW
Polarity change of the field identification signal at Port_A:
0: as detected in the field detection
1: inverted
−
25 to 16
−
reserved
7.12.3 VIDEO DATA STREAM HANDLING AT PORT D1_B
Table 68 Video data stream handling at port D1_B
OFFSET
NAME
BIT
TYPE
DESCRIPTION
(HEX)
54
VID_B
15 and 14
RW
Video data Port_B and PXQ_B select (PXQ goes always with data):
00: input, i.e. 3-state
01: reserved
10: output data stream is Y8C from BRS
11: output data stream is Y8C from HPS
Y8C codes:
Y8C_B
13
RW
0: no SAV and EAV data in the video data output stream
1: with SAV and EAV
−
12 and 11
10
−
reserved
PFID_B
RW
Polarity change of the field identification signal at Port_B
0: as detected in the field detection
1: inverted
−
9 to 0
−
reserved
1998 Apr 09
86
NXP [ NXP ]
