Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.12.6 VERTICAL AND HORIZONTAL SCALING
Table 72 HPS, vertical scaling
OFFSET
NAME
BIT
TYPE
DESCRIPTION
(HEX)
60
YACM
31
RW
Y (vertical) scaler Accumulation (calculation) Mode of vertical
arithmetic:
0: arithmetic operates as a linear phase interpolation (LPI)
1: arithmetic operates as accumulating FIR filter in vertical
direction.
YSCI
30 to 21
RW
Y scaler increment for vertical downscaling:
YSCI = INT [1024 × (NIL/NOL − 1) for YACM = 0 → LPI
YSCI = INT [1024 × (1 − NOL/NIL)] for
YACM = 1 → accumulation mode
NIL = number of qualified scaler input lines
NOL = number of output lines
YACL
YPO
20 to 15
14 to 8
RW
RW
accumulation sequence Length of the Y (vertical) processing:
Defines vertical accumulation sequence length of input lines
If accumulation FIR filter mode is selected YACM, YACL has to
fit to the vertical scaling factor (defined by YSCI)
vertical start phase for vertical scaling of the ODD field:
YPO = PHOL × 128
(PHOL represents a phase offset with values between logic 0
and logic 1, where the logic 1 represents a distance between two
consecutive lines of the input pattern)
YPE
7 to 1
RW
RW
vertical start phase for vertical scaling of the EVEN field:
YPE = PHOL × 128
(PHOL represents a phase offset with values between logic 0
and logic 1, where the logic 1 represents a distance between two
consecutive lines of the input pattern).
−
0
reserved
1998 Apr 09
90
NXP [ NXP ]
