Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
50
LLC_B
15
RW Line Locked Clock control for D1_B:
0: LLC_B set to input
1: LLC_B set to output, taken from LLC_A
RW Synchronization port_B configuration:
00: HS_B and VS_B are input (i.e. 3-state)
50
SIO_B
14 and
13
01: HS_B is output, HGT of HPS; VS_B is output, VGT of HPS
10: HS_B is output, RESET signal for a field memory; VS_B is input, vertical
sync signal for BRS this setting is needed for the field memory mode
11: HS_B is output, HGT of BRS; VS_B is output, VGT of BRS
RW Polarity of VS_B, if VS output:
0: direct from HPS or BRS, see SIO_B
1: inverted
50
50
50
PVO_B
PHO_B
12
11
RW Polarity of HS_B, if HS output is select by SIO_B:
0: direct from HPS or BRS, see SIO_B
1: inverted
SYNC_B 10 to 8
RW Sync edge selection and field detection mode internal sync signals SyncB
(Hb, Vb and Fb) if:
HS, VS are input: Hb/Vb/Fb derived from pins
HS, VS are output: HS/VS as select by SIO_B
000: Hb at rising edge of HS; Vb at rising edge of VS; Fb = HS × VS-rising,
directly
001: Hb at rising edge of HS; Vb at falling edge of VS; Fb = Hs × VS-falling,
directly
010: Hb at rising edge of HS; Vb at rising edge of VS; Fb = HS × VS-falling,
forced toggle
011: Hb at rising edge of HS; Vb at falling edge of VS; Fb = HS × VS-falling,
forced toggle
100: Hb at rising edge of HS; Vb at rising edge of VS
101: Hb at rising edge of HS; Vb at falling edge of VS; Fb = free toggle
110: Hb at rising edge of HS; Vb at rising and falling edge of Frame Sync at
the VS pin; Fb = direct FS
111: Hb, Vb and Fb derived from SAV and EAV decoded from the
data-stream at D1_B port. Not used if the MSB of HPSdatasel in Table 71
is set to logic 1
50
FIDESB 7 and 6 RW Field identification port_B edge select (ODD is defined by FID = 1, EVEN is
defined by FID = 0)
00: no interrupt condition
01: rising edge is interrupt condition
10: falling edge is interrupt condition
11: both edges are interrupt condition
−
5 to 0
−
reserved
1998 Apr 09
85
NXP [ NXP ]
