Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
DESCRIPTION
OFFSET
(HEX)
NAME
BIT
TYPE
INBOUND
OUTBOUND
58
BXO
16 to 7
RW horizontal offset, counted in
qualified LLC cycles, after
BXO defines a horizontal offset,
counted in LLC cycles, after
selected horizontal sync edge, till selected horizontal sync edge till
data is captured from DD1
data is read from the FIFO
in field memory mode the
following offsets depending on the
horizontal scaling ratio must be
selected to guarantee the correct
outrun behaviour of the scaler
(see Table 70). The video
window is select by ‘NumLines’,
‘NumBytes’, ‘pitch’ and ‘base
address’
BRS_H
6 to 4
RW horizontal downscaling
(see Section 7.10.1):
horizontal upscaling:
000: every pixel is captured
000: provide every sample once
001: every 2nd pixel is captured
001: provide every sample
twice
010: reserved
010: reserved
011: every 4th pixel is captured
011: provide every sample
4 times
100: reserved
100: reserved
101: reserved
110: reserved
101: reserved
110: reserved
111: every 8th pixel is captured
111: provide every sample
8 times
Read mode
3 and 2
RW reserved
00: line memory mode
01: field memory mode
10: direct mode with pixel
repetition for not qualified bytes.
11: direct with grey pixel (10H
for luminance and 80H for
chrominance values) for not
qualified bytes.
PCI format
1 and 0
RW output format PCI side:
00: YUV 4 : 2 : 2
input format PCI side:
00: YUV 4 : 2 : 2
01: reserved
01: Y8, only luminance
10: Y2, 2 MSBs of Y only
11: Y1, 1 MSB of Y only
10: reserved
11: reserved
1998 Apr 09
88
NXP [ NXP ]
